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Functions</h2></td></tr>
<tr class="memitem:gaf8e0bfe31c0fa2ca654c36715a3c13f8"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__v3__1.html#gaf8e0bfe31c0fa2ca654c36715a3c13f8">XScuGic_CfgInitialize</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr, <a class="el" href="struct_x_scu_gic___config.html">XScuGic_Config</a> *ConfigPtr, u32 EffectiveAddr)</td></tr>
<tr class="memdesc:gaf8e0bfe31c0fa2ca654c36715a3c13f8"><td class="mdescLeft">&#160;</td><td class="mdescRight">CfgInitialize a specific interrupt controller instance/driver.  <a href="group__scugic__v3__1.html#gaf8e0bfe31c0fa2ca654c36715a3c13f8">More...</a><br /></td></tr>
<tr class="separator:gaf8e0bfe31c0fa2ca654c36715a3c13f8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga48f9dd531aa861a74e6bd627943573ea"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__v3__1.html#ga48f9dd531aa861a74e6bd627943573ea">XScuGic_Connect</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr, u32 Int_Id, Xil_InterruptHandler Handler, void *CallBackRef)</td></tr>
<tr class="memdesc:ga48f9dd531aa861a74e6bd627943573ea"><td class="mdescLeft">&#160;</td><td class="mdescRight">Makes the connection between the Int_Id of the interrupt source and the associated handler that is to run when the interrupt is recognized.  <a href="group__scugic__v3__1.html#ga48f9dd531aa861a74e6bd627943573ea">More...</a><br /></td></tr>
<tr class="separator:ga48f9dd531aa861a74e6bd627943573ea"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad162acedbbd41fd890fc7f2225ed480b"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__v3__1.html#gad162acedbbd41fd890fc7f2225ed480b">XScuGic_Disconnect</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr, u32 Int_Id)</td></tr>
<tr class="memdesc:gad162acedbbd41fd890fc7f2225ed480b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Updates the interrupt table with the Null Handler and NULL arguments at the location pointed at by the Int_Id.  <a href="group__scugic__v3__1.html#gad162acedbbd41fd890fc7f2225ed480b">More...</a><br /></td></tr>
<tr class="separator:gad162acedbbd41fd890fc7f2225ed480b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac965b9e3ae7668a92cf07a65bde142cc"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__v3__1.html#gac965b9e3ae7668a92cf07a65bde142cc">XScuGic_Enable</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr, u32 Int_Id)</td></tr>
<tr class="memdesc:gac965b9e3ae7668a92cf07a65bde142cc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enables the interrupt source provided as the argument Int_Id.  <a href="group__scugic__v3__1.html#gac965b9e3ae7668a92cf07a65bde142cc">More...</a><br /></td></tr>
<tr class="separator:gac965b9e3ae7668a92cf07a65bde142cc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaafd153e16238a1189c513846675e096a"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__v3__1.html#gaafd153e16238a1189c513846675e096a">XScuGic_Disable</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr, u32 Int_Id)</td></tr>
<tr class="memdesc:gaafd153e16238a1189c513846675e096a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disables the interrupt source provided as the argument Int_Id such that the interrupt controller will not cause interrupts for the specified Int_Id.  <a href="group__scugic__v3__1.html#gaafd153e16238a1189c513846675e096a">More...</a><br /></td></tr>
<tr class="separator:gaafd153e16238a1189c513846675e096a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad71d2f581bdc46d89f38fced53e506bf"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__v3__1.html#gad71d2f581bdc46d89f38fced53e506bf">XScuGic_SoftwareIntr</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr, u32 Int_Id, u32 Cpu_Id)</td></tr>
<tr class="memdesc:gad71d2f581bdc46d89f38fced53e506bf"><td class="mdescLeft">&#160;</td><td class="mdescRight">Allows software to simulate an interrupt in the interrupt controller.  <a href="group__scugic__v3__1.html#gad71d2f581bdc46d89f38fced53e506bf">More...</a><br /></td></tr>
<tr class="separator:gad71d2f581bdc46d89f38fced53e506bf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga79abd6248cb578142e9c475f20dbeb06"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__v3__1.html#ga79abd6248cb578142e9c475f20dbeb06">XScuGic_SetPriorityTriggerType</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr, u32 Int_Id, u8 Priority, u8 Trigger)</td></tr>
<tr class="memdesc:ga79abd6248cb578142e9c475f20dbeb06"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sets the interrupt priority and trigger type for the specificd IRQ source.  <a href="group__scugic__v3__1.html#ga79abd6248cb578142e9c475f20dbeb06">More...</a><br /></td></tr>
<tr class="separator:ga79abd6248cb578142e9c475f20dbeb06"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6ed162180ffb45b082c2fbe23951ba13"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__v3__1.html#ga6ed162180ffb45b082c2fbe23951ba13">XScuGic_GetPriorityTriggerType</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr, u32 Int_Id, u8 *Priority, u8 *Trigger)</td></tr>
<tr class="memdesc:ga6ed162180ffb45b082c2fbe23951ba13"><td class="mdescLeft">&#160;</td><td class="mdescRight">Gets the interrupt priority and trigger type for the specificd IRQ source.  <a href="group__scugic__v3__1.html#ga6ed162180ffb45b082c2fbe23951ba13">More...</a><br /></td></tr>
<tr class="separator:ga6ed162180ffb45b082c2fbe23951ba13"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga40ef6d42e9520bb550163c3afd598980"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__v3__1.html#ga40ef6d42e9520bb550163c3afd598980">XScuGic_InterruptMaptoCpu</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr, u8 Cpu_Id, u32 Int_Id)</td></tr>
<tr class="memdesc:ga40ef6d42e9520bb550163c3afd598980"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sets the target CPU for the interrupt of a peripheral.  <a href="group__scugic__v3__1.html#ga40ef6d42e9520bb550163c3afd598980">More...</a><br /></td></tr>
<tr class="separator:ga40ef6d42e9520bb550163c3afd598980"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6146a0489a1c748ceeaee729639d48a7"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__v3__1.html#ga6146a0489a1c748ceeaee729639d48a7">XScuGic_Stop</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga6146a0489a1c748ceeaee729639d48a7"><td class="mdescLeft">&#160;</td><td class="mdescRight">It checks if the interrupt target register contains all interrupts to be targeted for current CPU.  <a href="group__scugic__v3__1.html#ga6146a0489a1c748ceeaee729639d48a7">More...</a><br /></td></tr>
<tr class="separator:ga6146a0489a1c748ceeaee729639d48a7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga945e029b4356be809020c81745c4a23b"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__v3__1.html#ga945e029b4356be809020c81745c4a23b">XScuGic_SetCpuID</a> (u32 CpuCoreId)</td></tr>
<tr class="memdesc:ga945e029b4356be809020c81745c4a23b"><td class="mdescLeft">&#160;</td><td class="mdescRight">This updates the CpuId global variable.  <a href="group__scugic__v3__1.html#ga945e029b4356be809020c81745c4a23b">More...</a><br /></td></tr>
<tr class="separator:ga945e029b4356be809020c81745c4a23b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6c30ba79ea9505dc29b9cac4deea3df8"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__v3__1.html#ga6c30ba79ea9505dc29b9cac4deea3df8">XScuGic_GetCpuID</a> (void)</td></tr>
<tr class="memdesc:ga6c30ba79ea9505dc29b9cac4deea3df8"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function returns the CpuId variable.  <a href="group__scugic__v3__1.html#ga6c30ba79ea9505dc29b9cac4deea3df8">More...</a><br /></td></tr>
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